Currently, integrated circuit (IC) layout is represented by polygons in standard formats like GDS-II (Graphic Data System) and OASIS (Open Artwork System Interchange Standard). Re-use of IC layout has been desired for many years. Because of technology scaling, re-use of IC layout has been limited or not possible. Therefore, the IC layout polygons need to be redrawn each time a technology changes, for example moving to smaller dimensions.
The Mead and Conway “lambda” rules were an early attempt at scaling, but were not useful outside an academic environment. None of these layout representations comprehend different interconnect structures as circuits scale. Two significant problems with scaling include:                1. Lithographic resolution is scaling at a different rate from overlay scaling, and        2. Device and interconnect structures change because of material properties and/or electric field requirements.        
It is within this context that the present invention arises.